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high speed, 3.3 v/5 v quad 2:1 mux/demux (4-bit, 1 of 2) bus switch adg3257 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no re- sponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2008 analog devices, inc. all rights reserved. 02914-001 features 100 ps propagation delay through the switch 2 switches connect inputs to outputs data rates up to 933 mbps single 3.3 v/5 v supply operation level translation operation ultralow quiescent supply current (1 na typical) 3.5 ns switching switches remain in the off state when power is off standard 3257 type pinout applications bus switching bus isolation level translation memory switching/interleaving functional block diagram 1 a 2a 3 a 4a s logic 1b 1 1b 2 2b 1 2b 2 3b 1 3b 2 4b 1 4b 2 be figure 1. general description the adg3257 is a cmos bus switch comprised of four 2:1 multiplexers/demultiplexers with high impedance outputs. the device is manufactured on a cmos process. this provides low power dissipation yet high switching speed and very low on resistance, allowing the inputs to be connected to the outputs without adding propagation delay or generating additional ground bounce noise. the adg3257 operates from a single 3.3 v/5 v supply. the control logic for each switch is shown in table 1 . these switches are bidirectional when on. in the off state, signal levels are blocked up to the supplies. when the power supply is off, the switches remain in the off state, isolating port a and port b. this bus switch is suited to both switching and level translation applications. it can be used in applications requiring level trans- lation from 3.3 v to 2.5 v when powered from 3.3 v. additionally, with a diode connected in series with 5 v v dd , the adg3257 may also be used in applications requiring 5 v to 3.3 v level translation. table 1. truth table be s function h x disable l l a = b 1 l h a = b 2 product highlights 1. 0.1 ns propagation delay through switch. 2. 2 switches connect inputs to outputs. 3. bidirectional operation. 4. ultralow power dissipation. 5. 16-lead qsop package.
adg3257 rev. e | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ..............................6 ? typical performance characteristics ..............................................7 ? test circuits ........................................................................................9 ? applications information .............................................................. 10 ? mixed voltage operation, level translation .......................... 10 ? memory switching ..................................................................... 10 ? outline dimensions ....................................................................... 11 ? ordering guide .......................................................................... 11 ? revision history 03/08rev. d to rev. e updated format .................................................................... universal changes to features .............................................................................1 changes to general description .......................................................1 changes to absolute maximum ratings ..........................................5 changes to pin configuration and function descriptions ...........6 changes to test circuits .....................................................................9 changes to ordering guide ...............................................................11 11/04rev. c to rev. d changes to specifications ...................................................................2 changes to ordering guide ...............................................................4 04/03rev. a to rev. b updated outline dimensions ............................................................8 06/02rev. 0 to rev. a edits to features ...................................................................................1
adg3257 rev. e | page 3 of 12 specifications v cc = 5.0 v 10%, gnd = 0 v. all specifications t min to t max , unless otherwise noted. table 2. parameter 1 symbol conditions 2 b version unit min typ 3 max dc electrical characteristics input high voltage v inh 2.4 v input low voltage v inl ?0.3 +0.8 v input leakage current i i 0 v in 5.5 v 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current i oz 0 a, b v cc 0.01 1 a maximum pass voltage 4 v p v in = v cc = 5 v, i o = ?5 a 3.9 4.2 4.4 v capacitance 4 a port off capacitance c a off f = 1 mhz 7 pf b port off capacitance c b off f = 1 mhz 5 pf a, b port on capacitance c a , c b on f = 1 mhz 11 pf control input capacitance c in f = 1 mhz 4 pf switching characteristics 4 propagation delay a to b or b to a, t pd t phl , t plh 5 v a = 0 v, c l = 50 pf 0.10 ns propagation delay matching 6 v a = 0 v, c l = 50 pf 0.0075 0.035 ns bus enable time be to a or b t pzh , t pzl c l = 50 pf, r l = 500 1 5 7.5 ns bus disable time be to a or b t phz , t plz c l = 50 pf, r l = 500 1 3.5 7 ns bus select time s to a or b enable t sel_en c l = 50 pf, r l = 500 8 12 ns disable t sel_dis c l = 50 pf, r l = 500 5 8 ns maximum data rate v a = 2 v p-p 933 mbps digital switch on resistance r on v a = 0 v i o = 48 ma, 15 ma, 8 ma, t a = 25c 2 4 i o = 48 ma, 15 ma, 8 ma 5 v a = 2.4 v i o = 48 ma, 15 ma, 8 ma, t a = 25c 3 6 i o = 48 ma, 15 ma, 8 ma 7 on-resistance matching r on v a = 0 v, i o = 48 ma, 15 ma, 8 ma 0.15 power requirements v cc 3.0 5.5 v quiescent power supply current i cc digital inputs = 0 v or v cc 0.001 1 a increase in i cc per input 4 , 7 i cc v cc = 5.5 v, one input at 3.0 v; others at v cc or gnd 200 a 1 temperature range is: vers ion b: C40c to +85c. 2 see test circuits section. 3 all typical values are at t a = 25c, unless otherwise noted. 4 guaranteed by design, not subject to production test. 5 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little prop agation delay to the system. propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 propagation delay matching between channels is calculated from on-resistance matching of worst-c ase channel combinations and l oad capacitance. 7 this current applies to the control pins only and represents the current required to switch internal capacitance at the specif ied frequency. the a and b ports contribute no significant ac or dc currents as they transition.
adg3257 rev. e | page 4 of 12 v cc = 3.3 v 10%, gnd = 0 v. all specifications t min to t max , unless otherwise noted. table 3. parameter 1 symbol conditions 2 b version unit min typ 3 max dc electrical characteristics input high voltage v inh 2.0 v input low voltage v inl ?0.3 +0.8 v input leakage current i i 0 v in 3.6 v 0.01 1 a off state leakage current i oz 0 a, b v cc 0.01 1 a on state leakage current i oz 0 a, b v cc 0.01 1 a maximum pass voltage 4 v p v in = v cc = 3.3 v, i o = ?5 a 2.3 2.6 2.8 v capacitance 4 a port off capacitance c a off f = 1 mhz 7 pf b port off capacitance c b off f = 1 mhz 5 pf a, b port on capacitance c a , c b on f = 1 mhz 11 pf control input capacitance c in f = 1 mhz 4 pf switching characteristics 4 propagation delay a to b or b to a, t pd t phl , t plh 5 v a = 0 v, c l = 50 pf 0.10 ns propagation delay matching 6 v a = 0 v, c l = 50 pf 0.01 0.04 ns bus enable time be to a or b t pzh , t pzl c l = 50 pf, r l = 500 1 5.5 9 ns bus disable time be to a or b t phz , t plz c l = 50 pf, r l = 500 1 4.5 8.5 ns bus select time s to a or b enable t sel_en c l = 50 pf, r l = 500 8 12 ns disable t sel_dis c l = 50 pf, r l = 500 6 9 ns maximum data rate v a = 2 v p-p 933 mbps digital switch on resistance r on v a = 0 v, i o = 15 ma, 8 ma, t a = 25c 2 4 v a = 0 v, i o = 15 ma, 8 ma 5 v a = 1 v, i o = 15 ma, 8 ma, t a = 25c 4 7 v a = 1 v, i o = 15 ma, 8 ma 8 on-resistance matching r on v a = 0 v, i o = 15 ma, 8 ma 0.2 power requirements v cc 3.0 5.5 v quiescent power supply current i cc digital inputs = 0 v or v cc 0.001 1 a increase in i cc per input 4 , 7 i cc v cc = 3.3 v, one input at 3.0 v; others at v cc or gnd 200 a 1 temperature range is: vers ion b: ?40c to +85c. 2 see test circuits section. 3 all typical values are at t a = 25c, unless otherwise noted. 4 guaranteed by design, not subject to production test. 5 the digital switch contributes no propagation delay other than the rc delay of the typical r on of the switch and the load capacitance when driven by an ideal voltage source. because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little prop agation delay to the system. propagation delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 6 propagation delay matching between channels is calculated from on-resistance matching of worst-c ase channel combinations and l oad capacitance. 7 this current applies to the control pins only and represents the current required to switch internal capacitance at the specif ied frequency. the a and b ports contribute no significant ac or dc currents as they transition.
adg3257 rev. e | page 5 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v cc to gnd ?0.3 v to +6 v digital inputs to gnd ?0.3 v to +6 v dc input voltage ?0.3 v to +6 v dc output current 100 ma operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c qsop package ja thermal impedance 149.97c/w lead soldering lead temperature, soldering (10 sec) 300c ir reflow, peak temperature (<20 sec) 220c soldering (pb-free) reflow, peak temperature 260(+0/?5)c time at peak temperature 20 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sec- tion of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg3257 rev. e | page 6 of 12 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 1b 1 1b 2 1a 2b 2 2b 1 s be 4b 1 4b 2 10 9 2a 3b 2 nd 3a 3b 1 4a v cc top view (not to scale) adg3257 02914-002 g figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 s port select. 2, 3, 5, 6, 10, 11, 13, 14 1b 1 , 1b 2 , 2b 1 , 2b 2 , 3b 2 , 3b 1 , 4b 2 , 4b 1 port b, inputs or outputs. 4, 7, 9, 12 1a, 2a, 3a, 4a port a, inputs or outputs. 8 gnd negative power supply. 15 be output enable (active low). 16 v cc positive power supply.
adg3257 rev. e | page 7 of 12 0 typical performance characteristics 12 8 4 16 20 012345 v a /v b (v) r on ( ? ) t a = 25c v cc = 5.0v v cc = 4.5v v cc = 5.5v 02 v a /v b (v) 914-003 figure 3. on resistance vs. input voltage 12 8 0 4 16 20 r on ( ? ) 0 0.5 1.0 1.5 2.0 3.0 2.5 t a = 25c v cc = 3.0v v cc = 2.7v v cc = 3.3v 02914-004 figure 4. on resistance vs. input voltage 0 20 r on ( ? ) 012345 v a /v b (v) 15 10 5 ?40c +85c +25c v cc = 5v 005 02914- v a /v b (v) 0 20 r on ( ? ) 0 0.5 1.0 1.5 2.0 3.0 2.5 figure 5. on resistance vs. input voltage for different temperatures 15 10 5 ?40c +85c +25c v cc = 3v 02914-006 figure 6. on resistance vs. input voltage for different temperatures frequency (khz) 10m current (a) 1m 100 10 1 100n 10n t a = 25c v cc = 5v v cc = 3v 0.1 1 10 100 1k 10k 02914-007 figure 7. i cc vs. enable frequency input voltage (v) output voltage (v) 5 4 3 2 1 0 t a = 25c v cc = 4.5v v cc = 5.0v v cc = 5.5v 012345 02914-008 figure 8. maximum pass voltage
adg3257 rev. e | page 8 of 12 output voltage (v) 3.6 3.0 2.0 1.0 0 v cc = 3.6v v cc = 3.3v v cc = 3.0v t a = 25c 02914-009 input voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 figure 9. maximum pass voltage 40mv/div 267ps/div 20db attenuation t a = 25c v cc = 5v v in = 2v p-p 622mbps 0 2914-010 figure 10. 622 mbps eye diagram 20db attenuation t a = 25c v cc = 5v v in = 2v p-p 933mbps 40mv/div 180ps/div 02914-011 figure 11. 933 mbps eye diagram
adg3257 rev. e | page 9 of 12 test circuits s1 dut gnd open pulse generator 1 v in r t 3 v cc v out c l 2 r l r l 2 v cc 1 pulse generator for all pulses: t f < 2.5ns, t r < 2.5ns. 2 c l = includes board, stray, and load capacitances. 3 r t is the termination resistor; should be equal to z out of the pulse generator. 0 2914-012 figure 12. load circuit 0v v ih v t t phl t plh switch input v oh v t v ol output 0 2914-013 figure 13. propagation delay enable disable 0v 0v 0v s1 @ 2v cc v t v oh ? v s1 @ 2v cc low t pzl t pzh control inputs t phz t plz v t v cc v ih v t v cc v ol + v v ol v oh output output 02914-014 figure 14. select, enable, and disable times table 6. switch s1 condition test s1 t plh , t phl open t plz , t pzl 2 v cc t phz , t pzh gnd t sel open table 7. test conditions symbol v cc = 5 v 10% v cc = 3.3 v 10% unit r l 500 500 v 300 300 mv c l 50 50 pf
adg3257 rev. e | page 10 of 1 2 applications information mixed voltage operation, level translation bus switches can be used to provide a solution for mixed voltage systems where interfacing bidirectionally between 5 v and 3.3 v devices is required. to interface between 5 v and 3.3 v buses, an external diode is placed in series with the 5 v power supply as shown in figure 15 . be 5v 3.3v 3.3v v cc = 5 v 5v memory 5v i/o 3.3v cpu/dsp/ microprocessor/ memory 4-015 3.3v 0291 figure 15. level translation between 5 v and 3.3 v devices the diode drops the internal gate voltage down to 4.3 v. the bus switch limits the voltage present on the output to v cc ? external diode drop = v th therefore, assuming a diode drop of 0.7 v and a v th of 1 v, the output voltage is limited to 3.3 v with a logic high. 3.3v 0v 5v v out 5v supply adg3257 2.5v 2.5v switch output switch input v in 02914-016 figure 16. input voltage to output voltage similarly, the device could be used to translate bidirectionally between 3.3 v to 2.5 v systems. in this case, there is no need for an external diode. the internal v th drop is 1 v, so with a v cc = 3.3 v the bus switch limits the output voltage to v cc ? 1 v = 2.3 v v 3 .3 v 2 .5 v 3.3v 2.5v 0v 3.3v out switch output switch input v in 3.3v supply 02914-017 figure 17. 3.3 v to 2.5 v level translation using the adg3257 bus switch memory switching this quad bus switch may be used to allow switching between different memory banks, thus allowing additional memory and decreasing capacitive loading. figure 18 illustrates the adg3257 in such an application. sdram no. 1 sdram no. 2 sdram no. 7 sdram no. 8 be s logic 02914-018 figure 18. allows additional memory modules without added drive or delay
adg3257 rev. e | page 11 of 12 compliant to jedec standards mo-137-ab outline dimensions 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.197 0.193 0.189 0.158 0.154 0.150 0.244 0.236 0.228 figure 19. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches ordering guide model temperature range packag e description package option adg3257brq C40c to +85c 16-lead shri nk small outline package [qsop] rq-16 adg3257brq-reel C40c to +85c 16-lead shrink small outline package [qsop] rq-16 ADG3257BRQ-REEL7 C40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg3257brqz 1 C40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg3257brqz-reel 1 C40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg3257brqz-reel7 1 C40c to +85c 16-lead shrink small outline package [qsop] rq-16 1 z = rohs compliant part.
adg3257 rev. e | page 12 of 12 notes ?2002 C 2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02914-0- 3 /08(e)

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